1. Field of Invention
The present invention generally relates to a boundary scan test interface circuit, and more particularly to the boundary scan test interface circuit for reducing the number of horizontal routes between a dynamic random access (DRAM) and a printed circuit board (PCB).
2. Description of Prior Art
Along with the rapid development of science and technology at the present, semiconductor memories are necessary devices for an electrical apparatus. For providing a larger storage size, a semiconductor memory has many address pins and control pins for addressing a plurality of memory cells in the semiconductor memory by a user. Accordingly, when a boundary scan test is processed on the semiconductor memory (such as a dynamic random access memory, (DRAM)), there are many horizontal routes connected to the address pins and control pins are needed. That is, a circuit size for the electrical apparatus having the DRAM is increased, and the prime cost of the electrical apparatus is increased correspondingly.